1. Technical Field
The disclosure relates to an electrically connected structure and more particularly to a through-silicon via.
2. Related Art
The semiconductor industry adopts through-silicon vias (TSVs) to connect vertically stacked chips. As a result, the length of the leads between the chips is shortened, the dimension of the devices is reduced, and the three-dimensional stacked framework of the chips is established.
TSV structures require high thermo-mechanical reliability between batches for mass production. Due to the differences in the coefficients of thermal expansion (CTE) of a filling material in the TSVs and of the silicon substrate, the internal stress of the TSVs usually leads to plastic deformation, stress-induced voiding, and stress migration. Furthermore, the stress at the interface of the TSVs causes peeling and popping up of the filled materials (that is so called copper pumps).
Other than thermo-mechanical reliability issues, electrical conductivity of the TSVs should also be taken into consideration. Hence, not only the filling materials for the TSVs but also the filling method applied to fill the TSVs need to be wisely selected to enhance the reliability of TSVs.